The present invention generally relates to the field of asynchronous static memory and more particularly to a dual threshold voltage sense amplifier for improving the read speed in asynchronous static memory without substantially increasing the core cell dimension or the overall design size.
In existing asynchronous static memory designs, the prevalent architecture employs a single NMOS (N-channel Metal Oxide Semiconductor) transistor to connect each core memory cell to the read bit line as shown in FIG. 1. This approach seeks to minimize the core cell dimension by using one transistor and one read word line. However, due to the finite threshold voltage of the NMOS transistor, the core cell, by itself, cannot drive the read bit line to full Vdd. Instead, a pair of inverters must be used as a sticky latch to pull the read bit line rail to rail. Furthermore, the rise time of the bit line waveform is typically slower than the fall time because the NMOS driving strength reduces as the bit line voltage rises near the threshold voltage.
Typical sense amplifiers utilize a simple inverter gate with its logic threshold set to a level that yields equal rise and fall times. These rise and fall times can be very large in the conventional single threshold design under certain conditions, for example, when the applied Vdd approaches the NMOS threshold voltage. The two separate threshold level approach allows for independent adjustment of the rise and fall times. However, any improvement in the rise time using the two separate threshold level approach is offset by a larger fall time. This is because the sense amplilier""s logic threshold level is required to be low enough that it can still trigger correctly even at the lowest applied Vdd, causing the fall time to stretch much longer than necessary to detect a logic zero.
Consequently, it is desirable to provide a dual threshold voltage sense amplifier that is capable of separating the rise time threshold from the fall time threshold, creating a dual sensing threshold voltage. In particular, it is desirable to provide a dual threshold voltage sense amplifier capable of providing a lower threshold for the rise time and a higher threshold for the fall time, thereby reducing the fall time and improving the read speed in asynchronous static memory without substantially increasing the core cell dimension or the overall design size.
Accordingly, the present invention is directed to a dual threshold voltage sense amplifier that is capable of separating the rise time threshold from the fall time threshold, creating a dual sensing threshold voltage. In one embodiment of the invention, the dual threshold voltage sense amplifier is capable of providing a lower threshold for the rise time and a higher threshold for the fall time, thereby reducing the fall time and improving the read speed in asynchronous static memory without substantially increasing the core cell dimension or the overall design size.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.